IJMTES – A NOVEL LOW POWER 8T SRAM DESIGN FOR REAL TIME APPLICATIONS

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : M Varatharaj, V Muralidharan, B Arunprakash

Volume 01 Issue 11  Year 2014  

ISSN no:  2348-3121

Page no: 1-4

Abstract— In this paper we propose a novel low power 8T static Random Access memory (SRAM) cell to enhance the stability and to save the power in various real time applications. For the validation of our proposed 8T SRAM cell, we are going to compare our results with reported data. The size of the proposed cell is comparable to the existing 8T SRAM cell with static 8T and 8T stability cell design rule. In this proposed 8T SRAM cell, write operation done by charging/discharging single bit line (BL), which results in reduction of dynamic power consumption. The proposed 8T SRAM cell reduces the dynamic power and leakage power while comparing with the existing 8T SRAM cell. The existing 9T, 10T and higher transistor count, SRAM cells enhance the read stability with area and power penalty. In this paper stability has been also analyzed.

Keywords— Dynamic power consumption, leakage power, stability, static noise margin

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