Journal Title : International Journal of Modern Trends in Engineering and Science
Author’s Name : Deepa.L, A.Thangamani , M.Varatharaj
Volume 01 Issue o3 March 2014
ISSN no: 2348-3121
Abstract—In this paper presents, the design of a novel on-chip network is to support a guaranteed traffic permutation in the multiprocessor system-on-chip applications. The dynamic path set up scheme provides run time path arrangement for conflict free permuted data. The pipelined circuit switching approach combined with dynamic path set up can be examined under multistage network topology. The circuit-switching approach offers a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks. The most important task in a network-on-chip is to design an on-chip switch to dynamically support guaranteed throughput under very tight on-chip constraints of power, timing, area, and time-to-market. The pre-configured data paths enable a throughput guarantee. By removing the excessive overhead of queuing buffers, a compact implementation is achieved and stacking multiple networks to support concurrent permutations in runtime is feasible. The test-chip validates the feasibility and efficiency of the proposed design.
Keywords— Adaptive systems, fault tolerance, Forward Error Correction (FEC), In-Line Test (ILT), Syndrome Storing-based Detection (SSD) and Network-on-chip (NoC)
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