IJMTES – IMPLEMENTATION OF DYNAMIC PATH NETWORK FOR MULTIPROCESSOR SYSTEM-ON-CHIP

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : Deepa.L, A.Thangamani , M.Varatharaj

Volume 01 Issue o3 March 2014

ISSN no:  2348-3121 

Page No:58-63

Abstract—In this paper presents, the design of a novel on-chip network is to support a guaranteed traffic permutation in the multiprocessor system-on-chip applications. The dynamic path set up scheme provides run time path arrangement for conflict free permuted data. The pipelined circuit switching approach combined with dynamic path set up can be examined under multistage network topology. The circuit-switching approach offers a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks. The most important task in a network-on-chip is to design an on-chip switch to dynamically support guaranteed throughput under very tight on-chip constraints of power, timing, area, and time-to-market. The pre-configured data paths enable a throughput guarantee. By removing the excessive overhead of queuing buffers, a compact implementation is achieved and stacking multiple networks to support concurrent permutations in runtime is feasible. The test-chip validates the feasibility and efficiency of the proposed design.

KeywordsAdaptive systems, fault tolerance, Forward Error Correction (FEC), In-Line Test (ILT), Syndrome Storing-based Detection (SSD) and Network-on-chip (NoC)

Reference

[1]. Chulwoo Kim, Jongsun Park, Junyoung Song, and Phi-Hung Pham,. (2013) Design and Implementation of an On Chip Permutation Network for Multiprocessor System-OnChip’ Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 21, No. 1, pp.173-177
[2]. C. Batten, N. Michael, M. Nikolov, G.E. Suh, and A. Tang, (2011),“Analysis of application-aware on-chip routing under traffic uncertainty,” in Proc. IEEE/ACM Netw. Chip (NoCS), , pp. 9–16.
[3]. A. Baghdadi, M. Jezequel , and H. Moussa, (2008) “Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder,” in Proc. ACM/ IEEE Design Autom. Conf. (DAC), pp. 429–434.
[4]. A. Baghdadi, M. Jezequel, H. Moussa, and O. Muller,(2007) “Butterfly and Benes-based on-chip communication networks for multiprocessor turbo decoding in Proc. Design, Autom. Test in Euro. pp. 654-659.
[5]. G. De Micheli and L. Benini, Networks on Chips: Technology and Tools (Systems on Silicon). San Fransisco, CA: Morgan Kaufmann, (2006).
[6]. D. Bertozzi, L. Benini, and G. De Micheli, “Error control schemes for on-chip communication links: The energy-reliability tradeoff,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., Vol. 24, No. 6, pp.818–831, Jun. (2005).
[7]. L. Li, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, “Adaptive error protection for energy efficiency,” in Proc. ICCAD, San Jose, CA, Nov. (2003), pp. 2–7.

Full Pdf Paper-Click Here

 

Scroll Up