IJMTES – DESIGN AND ANALYSIS OF LOW POWER SRAM CELL STRUCTURE

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : Jayabalaji.G, K.Gowri

Volume 01 Issue o4 April 2014

ISSN no:  2348-3121

Page no: 5-9

Abstract— SRAM is a CMOS ICs and it uses 8Transistor Sram to store a bit. This paper represents the simulation of different SRAM cells and their comparative analysis on parameters   Power Supply Voltage. All the simulations have  been  carried  out  Tanner EDA tool.  The most  research  on  the  power  consumption of  8T  SRAM  has  been  focused  on  the  static  power dissipation  and  the  power  dissipated  by  the  leakage current.  On  the  other  hand,  as  the  current  VLSI technology  scaled  down,  the  sub-threshold  current increases  which  further  increases  the  power consumption.  In  this paper we have proposed 8 Transistor  SRAM or  cells  using  MCML  technology  which  will reduce the leakage power in SRAM cell and will control the  sub-threshold  current.  The  results  of  8 transistor SRAM  cell  array  using MCML  technology  in  represents that there is a  significant  reduction  in  power  dissipation  and leakage current using MCML technology.

 Keywords8 transistor sram; mcml concept.

Reference 

[1]. C. H. Kim, H. Soeleman, and K. Roy, “Ultra-low-power DLMS adaptive filter for hearing aid applications,” IEEE Trans. Very Large Scale Integer.(VLSI) Syst., Vol. 11, No. 6, pp. 1058–1067, Dec. (2003).
[2]. S. Cserveny, L. Sumanen, J. M. Masgonty, and C. Piguet, “Locally switched and limited source-body bias and other leakage reduction techniques for a low-power embedded SRAM,” IEEE Trans. Circuits Syst. II,Exp. Briefs, Vol. 52, No. 10, pp. 636–640, Oct. (2005).
[3]. B. H. Calhoun and A. Chandrakasan, “A 256kB subthreshold SRAM using 65nm CMOS,” in Proc. Int. Solid- State Circuits Conf., Feb. (2006), pp. 2592–2601.
[4]. B. H. Calhoun and A. P. Chandrakasan, “A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation.” IEEE J. Solid-State Circuits,vol. 42, no. 3, pp. 680-688, Mar. (2007).
[5]. M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, “90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique,” IEEEJ. Solid-state Circuits, vol. 41, no. 3, pp. 705-711, Mar. (2006).
[6]. T. H. Kim, J. Liu, J. Keane, and C. H. Kim, “A 0.2 V, 480 kb sub threshold SRAM with 1 k cells per bitline for ultra-low-voltage computing,” IEEEJ. Solid-State circuits, Vol 43 No. 2, pp. 518–529, Feb. (2008).
[7]. R. J. Evans and P. D. Franzon, “Energy consumption modeling and optimization for SRAM’s,” IEEE J. Solid-State Circuits, vol. 30, no. 5,pp. 571–579, May(1995).
[8]. L. Chang, R. K. Montoye, Y. Nakamura, K. A. Batson, R. J. Eickemeyer, R. H. Dennard,W. Haensch, and D. Jamsek, “An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches,” IEEEJ. Solid-State Circuits, vol. 43, no. 4, pp. 956-963, Apr.(2008).
[9]. V. Joshi, R. Kanj, and V. Ramadurai, “A novel column-decoupled 8T cell for low-power differential and domino- based SRAM design,” IEEETrans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 5, pp. 869-882, May (2011).
[10]. B. Zhai, L. Nazhandali, J. Olson, A. Reeves, M. Minuth, R. Helfand, S. Pant, D. Blaauw, and T. Austin, “A 2.60pJ/Instsubthreshold sensorprocessor for optimal energy efficiency,” in VLSI Symp. Tech. Dig., 2006,pp. 154-155.
[11]. A. Wang and A. Chandrakasan, “A 180-mV subthreshold FFT processor using a minimum energy design methodology,” IEEE J. Solid-State Circuits, Vol. 40, No. 1, pp. 310–319, Jan. (2005).
[12]. A. T. Do, J. Y. S. Low, J. Y. L. Low, Z. H. Kong, X. Tan, and K. S. Yeo, “An8T differential SRAM with improved noise margin for bit-interleaving in 65 nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 58, No. 6,pp. 1252- 1263, Jun. (2011).

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