Journal Title : International Journal of Modern Trends in Engineering and Science
Author’s Name : S.Sathish kumar, V.Muralidharan
Volume 01 Issue o4 April 2014
ISSN no: 2348-3121
Page no: 10-13
Abstract— In adders the truncation and round off errors cannot be ignored. To rectify the errors in adders error tolerant adder (ETA) is proposed here. It increases the performance & reduces the delay by low power consumption. ETA mainly focuses on low power VLSI applications. ETA compensates the errors by adding the inputs parallel. In this paper to prove the efficiency of ETA normal CMOS XOR logic is replaced by PSEUDO NMOS XOR logic, PASS TRANSISTOR logic and COMPLEMENTARY PASS TRANSISTOR logic
Keywords— Adders; Error tolerance; Low power design; Technique; Cmos xor; Pseudo nmos xor; Pass transistor xor; Complementary pass transistor xor.
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