IJMTES – AN EFFICIENT DOUBLE EDGE TRIGGERING FLIP FLOP (MDETFF)

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : S.Santhoshkumar, L.Saranya

Volume 01 Issue o4 April 2014 

ISSN no:  2348-3121 

Page no: 22-26

Abstract An efficient double edge triggering flip flop (DETFF) for low-power and high-performance applications is presented in this paper. The aim of the DETFF is to reduce pipeline overhead. In its pulse generator, the four inverters are used to generate the inverted and delayed clock signals. The explicit pulse generator is simple and suitable for Modified double-edge triggering. However, the flip flop latency may be degraded due to the large capacitive loads output nodes. On top of that, MDETFF suffers from high leakage current. This is caused by a high-voltage drop across transistor. when they are off, the pulse generating stage, the sensing stage and the latching stage. The Modified double edge-triggered pulse generator produces a brief pulse signal synchronized at the rising and falling clock edges. Therefore, the conditional pre charging technique is applied in the sensing stage of MDETFF, to avoid redundant transitions at major internal nodes. As for output it only needs to be pre charged in the first cycle and remains at its high state for the remaining cycles. Since the pre charging activity is conditionally controlled, the critical pull down path is simplified, consisting of only one signal transistor. This helps to reduce the discharging time significantly. As such, the resulting sensing stage possesses low-power and high-speed feature.

Keywords Flip-Flop, High-speed, Leakage power

Reference

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