Journal Title : International Journal of Modern Trends in Engineering and Science
Author’s Name : R.Priyanka, S.Raja , S.Shajila Rani
Volume 01 Issue o4 April 2014
ISSN no: 2348-3121
Page no: 27-31
Abstract—This paper presents the evaluation and implementation of an 8-bit adaptable processor core to be part of the power-throughput-area efficient multimedia oriented reconfigurable architecture reconfigurable. The processor core design was custom implemented in IBM’s 90 nm CMOS technology and occupies 0.115 mm2 silicon area with approximately 70% area utilized by core circuits and it shows a peak throughput performance of 75 MOPS/m W. The result of benchmarking results show estimated throughputs of 9.5, 21.36, 39.78,170.88,and 4.54 MSamples/s for variants of 2-D discrete cosine transform (DCT), 4 × 4 H.264 integer transform and 2-D discrete wavelet transform, respectively. When compared against popular architecture, our analysis shows that the proposed design provides approximately 4–8 times higher throughput for 2-D DCT.
Keywords— CMOS, DCT, Throughput
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