IJMTES – MODIFIED RECONFIGURABLE ROUTER ARCHITECTURE FOR NETWORK-ON-CHIP

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : Minu Mathew, D Mugilan

Volume 01 Issue o5  Year 2014  

ISSN no:  2348-3121

Page no: 8-13

AbstractThe Network-on-Chip (NoC) is a new interconnection method, able to integrate a large number of IP cores while maintaining a high communication bandwidth between them. The NoC is made of a number of routers that are interconnected to each other. The router may homogeneous or heterogeneous. To obtain high flexibility and improve performance, MPSoCs will combine different types of processor cores and data memory units of different sizes, leading to heterogeneous architecture. But setting the buffer size at design time may lead to high power dissipation. So here we go for reconfigurable router architecture.  Actually the reconfigurable router is a heterogeneous router, but using reconfiguration technique, it is possible to dynamically change the buffer depth to each channel, in accordance with the necessity of the application and that increasing the power efficiency of the system. In this proposed architecture along with the reconfiguration unit, loopback module and ECC unit are included to avoid the data packet loss and to check the correctness of the data. Here analyzed the average power consumption by CMOS 90nm standard cell library using the Synopsys Design Compiler tool.

Keywords— Buffer depth; loopback module; network-on-chip (NoC); power dissipation; reconfigurable router.

Reference

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