Journal Title : International Journal of Modern Trends in Engineering and Science
Author’s Name : S.Sivasathya, T.Manikandan, DR.G.K.D Prasanna Venkatesan
Volume 01 Issue o5 Year 2014
ISSN no: 2348-3121
Page no: 244-249
Abstract—The demand for high speed comparators will increase the efficient operations of ADC architectures. The double tail comparator is a newly proposed that operates with reduced delay in 65-nm CMOS technology with a power supply of 0.28mW.The layout simulation in Microwind software 3.1 confirm the analysis results of double tail comparator. The major objective of the paper aims at analyzing the efficiency of Successive Approximation Register as it is the slowest Analog-to-Digital comparator by implementing the double tail comparator in it. This analysis aims at reducing the power consumption and delay of SAR. Its observed that SAR uses only 126mw of power supply and delay 9.565ns when Double tail comparator is Implemented.
Keywords—Analog to digital comparator, double tail comparator, Successive approximation Register.
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