Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : S.Sivasathya, T.Manikandan, DR.G.K.D Prasanna Venkatesan

Volume 01 Issue o5  Year 2014  

ISSN no:  2348-3121  

Page no: 244-249

Abstract—The demand for high speed comparators will increase the efficient operations of ADC architectures. The double tail comparator is a newly proposed that operates with reduced delay in 65-nm CMOS technology with a  power supply of 0.28mW.The layout simulation in Microwind software 3.1 confirm the analysis results of double tail comparator. The major objective of the paper aims at analyzing the efficiency of Successive Approximation Register as it is the slowest Analog-to-Digital comparator by implementing the double tail comparator in it. This analysis aims at  reducing the power consumption and delay of SAR. Its observed that SAR uses only 126mw of power supply and delay 9.565ns when Double tail comparator is Implemented.

Keywords—Analog to digital comparator, double tail comparator, Successive approximation Register.


[1]. Bernhard Wicht, Member, IEEE, Thomas Nirschl, and Doris SchmittLandsiedel, Member, IEEE,” Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier”.
[2].Pedro M. Figueiredo, Member, IEEE, and João C. Vital, Member, IEEE,”Kickback Noise Reduction Techniques for CMOS Latched Comparators”.
[3].Amin Nikoozadeh, Student Member, IEEE, and Boris Murmann, Member, IEEE,”An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch”.
[4].Yusuke Okaniwa, Hirotaka Tamura, Member, IEEE, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Member, IEEE, Nestoras Tzartzanis, Member, IEEE, William W. Walker, Member, IEEE, and Tadahiro Kuroda, Senior Member, IEEE,” A 40-Gb/s CMOS Clocked Comparator With Bandwidth Modulation Technique”
[5]. Pierluigi Nuzzo, Student Member, IEEE, Fernando De Bernardinis, Pierangelo Terreni, and Geert Van der Plas, Member, IEEE ,”Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures”.
[6].Jun He, Sanyi Zhan, Degang Chen, Senior Member, IEEE, and Randall L. Geiger, Fellow, IEEE,” Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators”.
[7]. Jaeha Kim, Member, IEEE, Brian S. Leibowitz, Member, IEEE, Jihon Ren, Member, IEEE, and Chris J. Madden, Member, IEEE,” Simulation an Analysis of Random Decision Errorsin Clocked Comparators”
[8].B.Goll and H.Zimmermann,”A Comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65”,IEEE Trans. Circuits Syst.II.
[9].S.U.Ay,”A sub-I volt 10-bit supply boosted SAR ADC design in standard CMOS”, Int J.Analog Integr.Circuits Signal Process.
[10].H.Lee,”A 12-b 600ks/s digitally self-calibrated pipelined algorithmic ADC”, IEEE J.Solid-State Circuits.Vol.29,pp.509-515.
[11].S.Sutarja and P.Gray,”A pipelined 13-bit,250ks/s, 5V analog to digital comparator,”IEEE J.Solid State Circuits,pp.1316-1323,Dec (1988).
[12] .K.Uyttenhove and M.S.J S teyaert,”Speed-power accuracy tradeoff in high-speed CMOS ADCs”,IEEE Trans.Circuits Syst.II,Analog Digit. Signal Process., Vol.49, No.3,pp.280-287,Mar.(2002).
[13].M.J.M Pelgrom, A.C.J Duinmaijer, and A.P.G Weblbers,”Matching Properties of MOS transistors,”IEEE J.Solid-State Circuits, Vol.24, pp.1433-1439, Oct (1995).
[14].L.Sumanan, M.Waltari, VV.HAakkarainen, and K.halonen,”CMOS Dynamic Comparators for pipeline A/D Converters,” May (2002),pp.V-157-160.
[15]. B.Razavi and B.A Wooley,”Design techniques for high-speed high-resolution comparators, ”IEEE J.Solid-State Circuits,Vol.27, No.6,pp.1916-1926.
[16].Y.Wong, M.Cohen and P.Abshire,”A 1.2GHz comparator with adaptable offset in 0.35µm CMOS,”IEEE Trans Circuits Sys.I, Reg.Papers,Vol.55,pp. 2584-2594.

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