IJMTES – ANALYSIS AND DESIGN OF LOW POWER FLIP-FLOP BASED ON SLEEPY STACK APPROACH

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : K Banupriya | P Sindhu | Karthikeyan L M

Volume 02 Issue 10  Year 2015

ISSN no: 2348-3121

Page no: 1-4

Abstract Low power is an important principal theme in today’s electronics industry. So this Low Power Pulse Triggered Flip Flop reviews various methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of  the techniques that have been proposed to overcome these difficulties. This paper concludes with the future challenges that must been met to design low power, high performance systems. In the existing method conventional explicit type pulse triggered FF (P-FF) design with clock gating technique are used. This method has been some disadvantages like high leakage power and delay . To obtain balanced performance among power, delay, and area, design space exploration is also a widely used. In a synchronous circuit dynamic power is consumed by a major source of clock power. Clock-gating technique was used to reduce clock power. Thus significant amount of power consumption is reduced by using clock gating technique. The proposed sleepy stack approach with edge trigger flip-flop design is used to solve the leakage power problem and reduce delay and current with different voltages. Because sleepy stack mode will employ to save the leakage power.

Keywords— Flip-Flop, clock gating, edge trigger design, sleepy stack approach

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