Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : Monisha D | Arul Karthick V J

Volume 02 Issue 12  Year 2015 

ISSN no: 2348-3121  

Page no: 57-59

Abstract Polar codes represent an emerging class of error-correcting codes with power to approach the capacity of a discrete memory less channel. The main objective is to perform error correction and detection. The proposed new efficient encoder allows high-throughput encoding with small hardware complexity, it can be systematically applied to the design of any polar code and to any level of parallelism. The delay elements can be reduced by new parallel pipelined architecture. This particular architecture uses folding transformation technique as well as register minimization. Pipelining and parallel processing is used to reduce the power consumption.

Keywords— Polar codes, polar encoder, Very Large Scale Integration (VLSI) optimization


[1] Hoyoung yoo and in-cheol park,”partially parallel encoder architcture for long polar codes,”IEEE transactions on circuits.,Vol.62,No.3,mar.(2015).
[2] R.Mori and T. Tanaka, “Performance of polar codes with the construction using density evolution,” IEEE Commun. Lett., Vol. 13, No. 7, pp. 519–521, Jul. (2009).
[3] S. B. Korada, E. Sasoglu, and R. Urbanke, “Polar codes: Characterization of exponent, bounds, constructions,” IEEE Trans. Inf. Theory, Vol. 56,No. 12, pp. 6253–6264, Dec. (2010).
[4] I. Tal and A. Vardy, “List decoding of polar codes,” in Proc. IEEE ISIT,(2011), pp. 1–5.
[5] K. Chen, K. Niu, and J. Lin, “Improved successive cancellation decoding of polar codes,” IEEE Trans. Commun., Vol. 61, No. 8, pp. 3100–3107, Aug. (2013).
[6] G. Sarkis and W. J. Gross, “Polar codes for data storage applications,” in Proc. ICNC, 2013, pp. 840– 844.
[7] G. Sarkis, P. Giard, A. Vardy, C. Thibeault, and W.J. Gross, “Fast polar decoders: Algorithm and implementation,” IEEE J. Sel. Areas Commun.,Vol. 32, No. 5, pp. 946–957, May (2014).
[8] G. Berhault, C. Leroux, C. Jego, and D. Dallet, “Partial sums generation architecture for successive cancellation decoding of polar codes,” in Proc.IEEE Workshop SiPS, Oct. (2013), pp. 407–412.
[9] B. Yuan and K. K. Parhi, “Low-latency successive-cancellation polar decoder architectures using 2-bit decoding,” IEEE Trans. Circuits Syst.I, Reg. Papers, Vol. 61, No. 4, pp. 1241–1254, Apr. (2014).
[10] C. Leroux, A. J. Raymond, G. Sarkis, and W. J. Gross, “A semiparallel successive-cancellation decoder for polar codes,” IEEE Trans. Signal Process., Vol. 61, No. 2, pp. 289–299, Jan. (2013).
[11] A. J. Raymond and W. J. Gross, “Scalable successive-cancellation hardware decoder for polar codes,” in Proc. IEEE GlobalSIP, Dec. (2013), pp. 1282–1285.
[12] U. U. Fayyaz and J. R. Barry, “Low-complexity soft-output decoding of polar codes,” IEEE J. Sel. Areas Commun., Vol. 32, No. 5, pp. 958–9664.
[13] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation.Hoboken, NJ, USA: Wiley, (1999).

Full Pdf Paper: Click Here