Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : Arsha P S | Devika R G

Volume 02 Issue 12  Year 2015

ISSN no: 2348-3121

Page no: 24-29

Abstract Several new generation wideband data communication systems nowadays, have adopted Orthogonal Frequency division Multiplexing technique. The core processing block of an OFDM system are the Fast Fourier Transform (FFT) block and the Inverse Fast Fourier Transform (IFFT). Therefore, special attention needs to be given to optimize these block. Hence, utilizing low power, area efficient as well as high speed multipliers and adders in Fast Fourier Transform will ensure enhanced performance and efficiency. The FFT/IFFT processors are commonly implemented with complex multipliers; a complex multiplier is equivalent to four real multipliers and two real adders, and a ROM to store the twiddle factors. The ROM in this type of implementation takes most of the chip area, consumes more power and degrades the speed.  Hence poor performance of the FFT in terms of power, speed, and area can be seen. The size of ROM in the multiplier based implementation for the twiddle factors becomes the matter of concern with larger chip area. CORDIC is a fast, simple, efficient and powerful shift add algorithm to calculate the wide range of functions including trigonometric, logarithmic, hyperbolic and linear. It is commonly used when there is no hardware multiplier is available. The aim of this paper is to design and implement a CORDIC based radix-4 configurable FFT/IFFT algorithm in OFDM systems. The FPGA implementation is performed using Very High Speed Integrated Circuit (VHSIC) Hardware Descriptive Language (VHDL).The performance of the coding is analyzed from the result of timing simulation using Xilinx ISE Design Suite 14.5 and Modelsim SE 6.5b.

Keywords— Orthogonal Frequency division Multiplexing; CORDIC; FPGA


[1] Amaresh Kumar, U.N. Tripathi, Roopak Kumar Verma, Manish Mishra,“64 Point Radix-4 FFT Butterfly Realization using FPGA”International Journal of Engineering and Innovative Technology (IJEIT) Volume 4, Issue 4, October (2014).
[2] Pramod Kumar Meher, Sang Yoon Park.’ CORDIC Designs for Fixed Angle of Rotation’; IEEE Transactions On Very Large Scale Integration (VLSI) Systems, VOL. 21, NO. 2, February (2013).
[3] Srinivasa Murthy H N, Roopa M, ’FPGA Implementation of Sine and Cosine Generators’, International Journal of Innovative Technology and Exploring Engineering(IJITEE) ISSN, Volume-1, Issue-6, November (2012).
[4] Rohit Shukla and Kailash Chandra Ray,’ Low Latency Hybrid CORDIC Algorithm’, IEEE Transactions On Computers, May (2012).
[5] M. Mohamed Ismail, Dr. M.J.S Rangachar and Dr.Ch. D.V. Paradesi Rao “VLSI Implementation of OFDM using Efficient Mixed-Radix 8-2 FFT Algorithm with bit reversal for the output sequences”. International Journal of Electronics and Communication Engineering. Volume 5, Number 4 (2012).
[6] Chu Yu, Chen-Hen Sung, Chien-Hung Kuo, and Mao-Hsu Yen,and Sao-Jie Chen, “Design and Implementation of a Low-Power OFDM Receiver for Wireless Communications”, IEEE Transactions on Consumer Electronics, Vol. 58, No. 3, August (2012).
[7] Arioua M., Belkouch S., Agdad M., Hassani M. M., “VHDL implementation of an optimized 8-point FFT/IFFT processor in pipeline architecture for OFDM systems,” International Conference on Multimedia Computing and Systems (ICMCS), pp.1-5, April (2011).
[8] Manohar Ayinala, Michael Brown, and Keshab K. Parhi, “Pipelined Parallel FFT Architectures via Folding Transformation,” IEEE Trans. VLSI Syst, Jun. (2012).
[9] John G. Proakis, Dimitris G. Manolokis “Digital signal processing” Pearson prentice Hall, Inc (2008).
[10] N. Mahdavi, R. Teymourzadeh, IEEE Student Member, Masuri Bin Othman, “VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application,” The 5th Student Conference on Research and Development, pp. 1-4,11-12 Dec. (2007).

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