Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : Sheik Azhar | M S Anuradha

Volume 02 Issue 12  Year 2015 

ISSN no: 2348-3121

Page no: 41-46

Abstract The clock distribution network consumes nearly 70% of the total power consumed by the IC, since this is the only signal which has the highest switching activity. Normally for a multi clock domain network we develop a multiple PLL to cater the need, this project aim for developing a low power modified multiband network which will supply for the multi clock domain network. This project is highly useful and recommended for communication applications like Bluetooth, Zigbee. Frequency synthesizer is one of the important elements for wireless communication application. The speed of VCO and prescaler determines how fast the frequency synthesizer. The proposed modified multimodulus consumes less power taken as average and has a maximum operating frequency of 6.2 GHz respectively. Here DSCH and Microwind are used to implement the above design.

Keywords Multimodulus, Frequency Synthesizer, Prescaler, Power Consumption, PLL


[1] H.R.Rategh et al., “A CMOS frequency synthesizer with an injected locked frequency divider for 5-GHz wireless LAN receiver,” IEEE J. Solid-State Circuits, Vol. 35, No.5, pp. 780-787, May (2000).
[2] P.Y.Deng et al., “A 5 GHz frequency synthesizer with an injection locked frequency divider and differential witched capacitors,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 56, No.2, pp. 320-326, Feb. (2009).
[3] L. Lai Kan Leung et al., “A I-V 9.7-mW CMOS frequency synthesizer for IEEE 802.lIa transceivers, “IEEE Trans. Microw. Theory Tech., Vol.56, No.1, pp.39-48, Jan. (2008).
[4] M. Alioto and G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic Digital Circuits, New York: Springer, (2005).
[5] Y. Ji-ren et al., “A true single-phase-clock dynamic CMOS circuit technique,” IEEE J. Solid-State Circuits, Vol. 24, No. 2, pp. 62-70, Feb. (1989).
[6] S. Pellerano et al., “A J3.5-mW 5 GHz frequency synthesizer with dynamic-logic frequency divider,” IEEE J. Solid-State Circuits, Vol. 39, No. 2, pp. 378-383, Feb.(2004).
[7] V. K. Manthena et al., “A low power fully programmable J MHz resolution 2.4 GHz CMOS PLL frequency synthesizer,” in Proc. IEEE Biomed. Circuits Conf, Nov. (2007).pp 187-19.
[8] S. Shin et al., “4.2 mW frequency synthesizer for 2.4 GHz Zig-Bee application with fast settling time Performance,” in IEEE MTT-S Int. Microw. Symp. Dig. , Jun. (2006), pp. 411–414.
[9] S. Vikas et al., “1 V 7-mW dual-band fast-locked Frequency Symp synthesizer,” in Proc. 15th ACM. VLSI, (2005), pp. 431–435.
[10] J. M. Rabaey et al., “Digital integrated circuits, a Design perspective,” in Ser. Electron and VLSI, 2nd Ed. Upper Saddle River, NJ: Prentice- Hall, (2003).
[11] X. P. Yu et al., “Design and optimization of the Extended true single-phase clock-based prescaler,” IEEE Trans. Micro. Theory Tech., Vol. 56, No. 11, pp. 3828– 3835, Nov. (2006).

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