IJMTES – LOW POWER CARRY SKIP ADDER USING SKIP LOGIC IN WIDE RANGE OF VOLTAGE LEVELS

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : M Indu | Dr D Somasundareswari

Volume 02 Issue 12  Year 2015 

ISSN no: 2348-3121  

Page no: 47-51

Abstract A carry skip adder (CSKA) structure has the high speed and very low power consumption. The speed of the structure is achieved by concatenation of all the blocks. The incrementation blocks are used to improve the efficiency of the carry skip adder structure. In existing method multiplexer logic is used, the proposed structure uses the AND-OR-Invert (AOI) and OR-AND-Invert (OAI) for the skip logic. The carry skip adder structure is realized with both fixed stage size and variable stage size where the delay is reduced, and speed is improved. A hybrid variable latency extension lowers the power consumption without affecting the speed of the circuit. The results are obtained using XILINX and it gives 42% and 37% improvements in the delay and energy of the structures. In addition to this structure, the power–delay product was low among all the structures, while having its energy–delay product was almost same as that of the conventional structure. Simulations on the proposed structure by using hybrid variable latency CSKA reduces the power consumption compared with the previous works and it produces a high speed.

Keywords— Carry Skip Adder (CSKA), AOI, OAI, energy efficient, high performance, hybrid variable latency adders

Reference

[1]. Koren, Computer Arithmetic Algorithms, 2nd ed. Natick, MA, USA: A K Peters, Ltd., (2002).
[2]. R. Zlatanovici, S. Kao, and B. Nikolic and koren,“Energy–delay optimization of 64-bit carry-lookahead adders with a 240 ps 90 nm CMOS design example,” IEEE J. Solid-State Circuits, Vol. 44, No. 2, pp. 569–583, Feb. (2009).
[3]. S. K. Mathew, M. A. Anders, B. Bloechel, T. Nguyen, R. K. Krishnamurthy, and S. Borkar, “A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS,” IEEE J. Solid-State Circuits, Vol. 40, No. 1, pp. 44–51, Jan. (2005).
[4]. V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, and R. Krishnamurthy, “Comparison of highperformance VLSI adders in the energy-delay space,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 13, No. 6, pp. 754–758, Jun. (2005).
[5]. B. Ramkumar and H. M. Kittur, “Low-power and areaefficient carry select adder,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 20, No. 2, pp. 371–375, Feb. (2012).
[6]. M. Vratonjic, B. R. Zeydel, and V. G. Oklobdzija, “Lowand ultra low-power arithmetic units: Design and comparison,” in Proc. IEEE Int. Conf. Comput. Design, VLSI Comput. Process. (ICCD), Oct. 2005, pp. 249–252.
[7]. C. Nagendra, M. J. Irwin, and R. M. Owens, “Areatime-power tradeoffs in parallel adders,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., Vol. 43, No. 10, pp. 689–702, Oct. (1996).
[8]. Y. He and C.-H. Chang, “A power-delay efficient hybrid carry- lookahead/carry-select based redundant binary to two’s complement converter,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 55, No. 1, pp. 336–346, Feb. (2008).
[9]. C.-H. Chang, J. Gu, and M. Zhang, “A review of 0.18μm full adder performances for tree structured arithmetic circuits,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 13, No. 6, pp. 686–695, Jun. (2005).
[10]. D. Markovic, C. C. Wang, L. P. Alarcon, T.-T. Liu, and J.M. Rabaey, “Ultralow-power design in near-threshold region,” Proc. IEEE, Vol. 98, No. 2, pp. 237–252, Feb.(2010).
[11]. R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge, “Near-threshold computing: Reclaiming Moore’s law through energy efficient integrated circuits,” Proc. IEEE, Vol. 98, No. 2, pp. 253–266, Feb. (2010).
[12]. S. Jain et al., “A 280 mV-to-1.2 V wide-operating-range IA-32 processor in 32 nm CMOS,” in IEEE Int. SolidState Circuits Conf. Dig. Tech. Papers (ISSCC), Feb.(2012), pp. 66–68.
[13]. R. Zimmermann, “Binary adder architectures for cellbasedVLSI and their synthesis,” Ph.D. dissertation,Dept. Inf. Technol. Elect. Eng., Swiss Federal Inst.Technol. (ETH), Zürich, Switzerland, (1998).
[14]. D. Harris, “A taxonomy of parallel prefix networks,” in Proc. IEEE Conf. Rec. 37th Asilomar Conf. Signals, Syst., Comput., Vol. 2. Nov. (2003), pp. 2213–2217.
[15]. P. M. Kogge and H. S. Stone, “A parallel algorithm for the efficient solution of a general class of recurrence equations,” IEEE Trans. Comput., Vol. C-22, No. 8, pp. 786–793, Aug. (1973).

Full Paper: Click Here