IJMTES – REDUCING POWER IN GLITCH FREE UNIVERSAL GATE USING DCDL TECHNIQUE

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : Gurupriya R

Volume 02 Issue 05  Year 2015

ISSN no: 2348-3121

Page no: 12-15

Abstract— Digitally controlled delay line is a digital circuit used to provide the desired delays for a circuit whose delay is controlled by a digital controlled word.. Glitches are the most considerable factor that limits the use of DCDL in many applications such as DLL and clock generators. The NOR-Based circuit eliminates the glitches. This circuit uses control bits which can be generated by using dual triggered flip-flop. This flip-flop consumes more power. In the proposed method, power consumption is reduced by using dual edge triggered sense amplifier flip-flop has been reduced using clock-gated sense-amplifier flip-flop. The simulations are done using Microwind analysis software tools. Our proposed system simulations are done under CMOS 0.12m technology and the results are compared with other conventional flip-flops. Hence, our proposed system is showing better output than the other flip-flops.

Keywords— All digital delay locked loop, delay cell, phase locked loop, digitally controlled delay line

Reference

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