Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : G V Manoj Gowtham

Volume 02 Issue 08  Year 2015

ISSN no: 2348-3121

Page no: 7-9

AbstractFrequency dividers are crucial circuits that are employed in PLLs and high-speed serialize/deserializers. The flip-flop-based frequency dividers are comprised of two D latches in cascade, and in a negative feedback configuration. The digital operation of this type of dividers provides the advantage of suppressing the sensitivity to waveform distortions. Furthermore, the flip-flop-based dividers achieve a wide bandwidth than other types of frequency dividers at low-to-medium range of frequencies.Frequency dividers play an important role in high speed communications systems. In particular, optical communication circuits demand frequency dividers capable of operating well above 10 GHz. This paper presents a high-speed DFAL flip-flop-based frequency divider incorporating a new high-speed latch topology, which provides satisfactory performance for frequencies up to 17 GHz. This circuit is designed and simulated in a standard 0.18μm CMOS process. This architecture is primarily a master-slave flip-flop with a negative feedback. This circuit works by continually toggling the output state after every clock cycle. The mechanism effectively causes the output to toggle between one and zero at a rate half that of the input clock. Thus frequency division is achieved. The designed circuit and the verification can be done in TANNER EDA.

Keywords Adiabatic, digital circuit, DFAL, frequency divider, low power


[1] A.G.Dickinson and J.S.Denker, “ Adiabatic dynamic logic”,Solid-StatesCircuits, IEEE Journal, Vol.30,Issue3, Mar., 1995,pp.311-315.
[2] Changhua Cao and KennethK.O, “APowerEfficient26-GHz32:1 Static Frequency Divider in 130-nmBulk CMOS”,IEEE Microwave and Wireless components letters VOL. 15, NO. 11, NOVEMBER (2005).
[3] HimanshuPuri, Kshitij Ghai, Kirti Gupta and Neeta Pandey,“A Novel DFAL based Frequency Divider”, in Proc. IEEE 2014International Conference on Signal Processing and Integrated Networks.
[4] Hamid Mahmoodi-Meimand, Ali Afzali-Kushaand Mehrdad Nourani, “Efficiency of Adiabatic Logic for Low-Power”, LowNoise VLSI Circuits and Systems, 2000. Proceedings of the43rdIEEE Midwest SymposiumVolume:1.
[5] N.S.S.Reddy, M.Satyam, and K.L.Kishore, ” Cascadable adiabatic logic circuits for low-power applications, IET Circuits”,Devices and Systems, Vol.2, No.6, pp.518–526, (2008).
[6] Nazrul Anuar, Yasuhiro Takahashi ,and Toshikazu Sekine, ”Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family”,Journal of Semiconductor Technology and Science,VOL.10, NO.1, MARCH,2010).
[7] Shipra Upadhyay, R.A.Mishra, R.K.Nagaria, and S.P.Singh “DFAL:Diode-Free Adiabatic Logic Circuits”, Hindawi Publishing Corporation ISRN Electronics, Volume (2013), ArticleID673601,12 pages.
[8] Y.Takahashi, Y.Fukuta, T.Sekine, and M.Yokoyama,“2PADCL: Two phasedrive adiabatic dynamic CMOS logic”, in Proc.IEEE APCCAS, Dec.,2006, pp.1486-1489.
[9] Y.Moon and D. K.Jeong, “ An efficient charge recovery logic circuit”,Solid-States Circuits., IEEE Journal, Vol.31,Issue4, Apr., 1996, pp.514-522.
[10]Y.Ye, and K.Roy, ”QSERL: Quasi-static energy recovery logic”, Solid-States Circuits.,IEEEJournal,Vol.36,Issue2, Feb., (2001), pp. 239-248.

Full Paper: Click Here


Scroll Up