IJMTES – DESIGN OF 16-BIT FLOATING POINT MULTIPLY AND ACCUMULATE UNIT

Journal Title : International Journal of Modern Trends in Engineering and Science

Paper Title : DESIGN OF 16-BIT FLOATING POINT MULTIPLY AND ACCUMULATE UNIT

Author’s Name : Saravanan R | Balaji P | Prabu Runnamed

Volume 03 Issue 01 2016

ISSN no:  2348-3121                                                                                                                                                   

Page no: 15-17

Abstract – In most systems using digital signal processing Multiply-Accumulate (MAC) is one of the main functions. The performance of the whole system depends on the performance of the MAC units. This paper presents the design and implementation of 16-bit floating point Multiply and Accumulate (MAC) unit. Generally MAC unit consists of three units – Floating-point multiplier, Adder and an Accumulator. The input takes form of half-precision format where there is 1-bit for sign, 8-bits for exponent and 7-bits for mantissa thereby making it a high performance unit. The design is coded in Verilog HDL and simulation is done using ModelSim. The proposed 16-bit floating point MAC unit is implemented on Xilinx Spartan 3E field programmable gate array (FPGA) device and synthesized with standard cell library.

Keywords— MAC, Floating point, critical time delay, FPGA

Reference

  1. Strenski.D, Cappello.J.D, “A practical measure of FPGA floating point acceleration for High Performance Computing”, Proceeding of 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp.160-167, 5-7 June 2013.
  2. Peter-Michael seidel and Guy Even, “On the Design of Floating-Point Adders”, in proceedings of the 15th IEEE symposium of Computer Arithmetic.
  3. Mohamed Al-Ashrafy, Ashraf Salem and Wagdi Anis, “An Efficient Implementation of Floating Point Multiplier”, proceeding of 2011 IEEE Saudi International Electronics , Communications and Photonics Conference (SIECPC), pp.1-5, April 2011. 
  4. Behrooz Parhami, ‘Computer Arithmetic: Algorithms and Hardware Designs’, 1st ed. Oxford: Oxford University Press, 2000
    IEEE Standards Board, IEEE-754, IEEE Standard for Binary Floating-Point Arithmetic, New York: IEEE, 1985.
  5. Lamiaa S.A.Hamid, Khaled A.Sheata, Hassan El-Ghitani, Mohamed Elsaid, “Design of Generic Floating Point Multiplier and Adder/Subtractor Units”, in proceedings of the 12th IEEE International Conference on Computer Modelling and Simulation, pp.615-618, March 2010.

Full Pdf-click here