IJMTES – A NOVEL METHOD FOR VLSI DESIGN OF PWM TRANSCEIVER USING TUNABLE SELF REFERENCED EDGE DETECTION

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : Nishanthi.R unnamed

Volume 03 Issue 02 2016

ISSN no:  2348-3121

Page no: 14-19

Abstract – A CMOS pulse width modulation (PWM) transceiver circuit that exploits the self-referenced edge detection technique is presented.  BY comparing the rising edge that is self-delayed by about 0.5T and the modulated falling edge in one carrier clock cycle, area-efficient and high robustness (against timing fluctuation) edge detection enabling PWM communication is achieved without requiring elaborate phase-locked loops. The previous method with PLL has difficulty in recovering clock signal when both rising and falling edges are modulated. Since the proposed Tunable self-referenced edge detection circuit has the capability of timing error measurement while changing the length of self-delay element. Finite State Machine (FSM) technique is mathematical model of computation used to both computer programs and sequential logic circuits. In this method used for reliability improvement, error check and correction associated with inter cycle edge detection is introduced and its effectiveness is verified by 1-bit PWM measurement.

KeywordsPulse width modulation; self-referenced edge detection; timing error measurement; FSM;

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