IJMTES – AN INNOVATION IN AREA OPTIMIZATION OF STAGE BASED OCV MODELING FOR A BETTER STA SIGN-OFF

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : R.Naveenkumar | K.Kalaichelvi | S.Rajesh Kumar | N.Arun Kumar unnamed

Volume 03 Issue 03 2016

ISSN no:  2348-3121

Page no: 6-9

Abstract – The design-cycle of VLSI-chips consists of different consecutive steps from high-level synthesis (functional design) to production (packaging).This project aims to implement a physical design flow from net list to gdsii that starts from floor plan, placement, CTS, routing and ends with physical verification. The main objective of this project is to fix the violations those results in the implementation of Leon processor such as crosstalk, slew violations, congestion and other signal integrity issues. Results show that the proposed steps eliminate these issues and clear the physical verification checks such as DRC, LVS static and IR and antenna design rule. Further the resultant optimized design meets the timing constraints and minimizes area to obtain a design suitable for manufacture.

Keywords— Signal Integrity, Crosstalk, CTS, Congestion, Slew violations

Reference

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