Journal Title : International Journal of Modern Trends in Engineering and Science
Volume 03 Issue 03 2016
ISSN no: 2348-3121
Page no: 19-21
Abstract – The Baugh-Wooley algorithm is a fine iterative algorithm for performing multiplication in digital signal processing typed applications. Decomposition sense is used with Baugh-Wooley algorithm to enhance the speed and to reduce the critical path delay. In this thesis a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The outcome is compare with booth multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3 device. The modi?ed-Booth algorithm is extensively used for high-speed multiplier circuits. In designs based on reduction trees with logarithmic logic depth, however, the reduced number of partial products has a imperfect impact on overall performance. The Baugh-Wooley algorithm is a different scheme for signed multiplication, but is not so widely adopted because it may be difficult to deploy on irregular reduction trees. We apply the Baugh-Wooley algorithm in an High Performance Multiplier (HPM) tree, which combines a regular layout with a logarithmic logic depth. We show for a range of worker bitwidths that, when implemented in 130-nm and 65-nm process technologies, the Baugh-Wooley multipliers exhibit similar delay, less power dissipation and smaller area foot-print than modified-Booth multipliers.
Keywords— Carry skip adder (CSKA); Energy Efficient; High Performance; Hybrid Variable Latency Adders; Wallace Tree Multiplier
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