IJMTES – ARITHMETIC MODEL FOR ARRAY BASED APPROXIMATE COMPUTING WITH MULTIPLIER AND SQUARER DESIGN

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : Priyanka R | Mahendrakumar S  unnamed

Volume 03 Issue 04 2016

ISSN no:  2348-3121

Page no: 19-22

Abstract – In CMOS technology and VLSI design, the power consumption becomes a major problem. In existing system, Array Based Approximate Arithmetic Computing (AAAC) has the building block of Error Compensation Unit (ECU).In this existing system multiplier and Squarer applications are designed to obtain optimal trade off between area, delay and energy consumption of AAAC circuits. In this system it occupies a larger area by which it increases the power consumption and delay. By the use of truncation it can improve the speed of the computation, but it has limitation that it does not consider the minimum bit error.
To overcome this, Error Compensation unit is designed using logic formulation to minimize delay and reduce area and also reduce power consumption compared to existing method. Multiplier and Squarer are coded in VHDL and simulated in ModelSim and synthesized in EDA tool Xilinx ISE 9.2i. Then this technique will be implemented in Spartan 3E.

Keywords— Booth Multiplier; Squarer; Compressor; Encoder 

Reference

  1. Y. H. Chen, ‘An accuracy-adjustment fixed-width booth multiplier based on multilevel conditional probability’, IEEE Transaction Very Large Scale Integration (VLSI) System, Vol 23, No.1, pp. 203-207,2014.
  2. H. A. Huang et Al. , ‘A self-compensation fixed-width Booth multiplier and its 128-point FFT applications’, Proc. IEEE ISCAS, pp. 3538-3541, 2006.
  3. Jeena Maria Cherian and B. Sireesha, ‘Design of high-accuracy fixed-width modified booth multiplier’, International Journal of Computer Science and Information Technology, Vol.3, pp.238-290, 2014.
  4. S. J. Jou, ‘Low-error reduced-width Booth multipliers for DSP applications’, IEEE Trans. Circuits Syst. I, Vol. 50, No. 11, pp. 1470–1474, 2003.
  5. T. S. Juang and S.F. Hsiao, ‘Low-error carry-free fixed-width multipliers with low-cost compensation circuits’, IEEE Trans. Circuits Syst.II, vol. 52, no. 6, pp. 299–303, 2005.
  6. S. R. Kuang et al , ‘Modified Booth multipliers with a regular partial product array’ , IEEE Trans. Circuits Syst. II,Vol. 56, No. 5, pp. 404–408, 2009.
  7. B. Shano and P. Li, ‘A model for array-based approximate arithmetic computing with application to multiplier and squarer design’ ,Low Power Electron Design, pp. 9-14 (2014).
  8. V. G. Oklobdzija et al ,‘A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach,’ IEEE Trans. Comput.,Vol. 45, No.3,pp 294–306,1996.

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