Journal Title : International Journal of Modern Trends in Engineering and Science
Volume 03 Issue 04 2016
ISSN no: 2348-3121
Page no: 19-22
Abstract – In CMOS technology and VLSI design, the power consumption becomes a major problem. In existing system, Array Based Approximate Arithmetic Computing (AAAC) has the building block of Error Compensation Unit (ECU).In this existing system multiplier and Squarer applications are designed to obtain optimal trade off between area, delay and energy consumption of AAAC circuits. In this system it occupies a larger area by which it increases the power consumption and delay. By the use of truncation it can improve the speed of the computation, but it has limitation that it does not consider the minimum bit error.
To overcome this, Error Compensation unit is designed using logic formulation to minimize delay and reduce area and also reduce power consumption compared to existing method. Multiplier and Squarer are coded in VHDL and simulated in ModelSim and synthesized in EDA tool Xilinx ISE 9.2i. Then this technique will be implemented in Spartan 3E.
Keywords— Booth Multiplier; Squarer; Compressor; Encoder
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