IJMTES – LOW-LATENCY WORMHOLE ROUTERS FOR ON-CHIP NETWORKS

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : N Rajesh Kumar | A Dhivya | K Kalaivani | R Sindhu  unnamed

Volume 03 Issue 06 2016

ISSN no:  2348-3121

Page no: 50-55

Abstract – On-chip routers typically have buffers devoted to their input or output ports for temporarily storing packets. Buffers, regrettably, consume significant portions of router area and power budgets. In previous design, a more number of buffer queues in the network are null and other queues are mostly busy and only 1 byte of data can be transferred in unidirection. In this article the design is implemented with sharing the buffers among the virtual channels, to maximize the utilization of buffer. This feature is more efficient, because they have high throughput and low queuing delays under heavy loads. Performance evaluation of the routing node in terms of latency is the characteristics of an efficient design of buffer in input module. Wormhole routing is a network flow control mechanism which decomposes a packet into smaller fluts and delivers the fluts in a pipelined fashion. It has better performance and less buffering requirements. We conclude that more bytes of data can be transferred bidirectionally without error by using error detection and correction.

KeywordsOn chip network, router architecture, shared buffer, wormhole routing 

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