IJMTES – DESIGN OF VARIABLE LATENCY BY PASS MULTIPLIER WITH ADAPTIVE HOLD LOGIC

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : Kiruthiga.S | Chandrasekaran.V  unnamed

Volume 03 Issue 06 2016

ISSN no:  2348-3121

Page no: 80-83

Abstract – Multiplication is important in arithmetic operations such as fourier transform, microprocessors, etc.  System performance is based on the multiplier throughput. Pmos transistor and Nmos transistor is affected by temperature instability. It affects the system performance. so it is necessary to design multiplier with reliability. In this the multiplier is designed with flipflop and AHL circuit. The number of clock cycle is high in fixed latency. In Variable latency the number of clock cycle is reduced. More number of zeros is inserted in the column by pass method so this reduces the switching activity. Hence the power consumption is reduced. In this paper variable latency column by pass multiplier is designed to reduce the timing wastage, performance degradation and to increase the speed of the circuit.

KeywordsMultiplier, Flipflop, AHL Circuit, Variable Latency 

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