Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : Kiruthiga.S | Chandrasekaran.V  unnamed

Volume 03 Issue 06 2016

ISSN no:  2348-3121

Page no: 80-83

Abstract – Multiplication is important in arithmetic operations such as fourier transform, microprocessors, etc.  System performance is based on the multiplier throughput. Pmos transistor and Nmos transistor is affected by temperature instability. It affects the system performance. so it is necessary to design multiplier with reliability. In this the multiplier is designed with flipflop and AHL circuit. The number of clock cycle is high in fixed latency. In Variable latency the number of clock cycle is reduced. More number of zeros is inserted in the column by pass method so this reduces the switching activity. Hence the power consumption is reduced. In this paper variable latency column by pass multiplier is designed to reduce the timing wastage, performance degradation and to increase the speed of the circuit.

KeywordsMultiplier, Flipflop, AHL Circuit, Variable Latency 


  1. Abrishami H, Hatami S, Amelifard B, and Pedram M (2008),“NBTI-aware Flip- Flop characterization and design,” in proc.44th ACM GLSVLSI, pp. 29-34.
  2. Chen et al Y (2010), ‘Variable-latency adder designs for low power and NBTI tolerance,” IEEE Trans.VLSI Systems,Vol.18, No.11,pp.1621-1624.
  3. Ing-Chao Lin, Yu-Hung Cho and Yi-Ming Yang (2014), ‘Aging-aware Reliable multiplier design with adaptive hold logic’,IEEE Trans.VLSI Systems, vol.61,No. 6 .
  4. Lee Y and Kim T (2011), “ A fine-grained technique of NBTI-aware Voltage scaling and body biasing for standard cell based designs,”in proc. ASPDAC, pp.603-608.
  5. Lin Y-N, Wen M-C, Wang S-J (2005), “Low power parallel multiplier With column by passing,” in proc, IEEE ISCAS, pp.1638-1641.
  6. Marculescu D K-C. Wu and (2009), “Joint logic restructuring and pin Reordering against NBTI- induced performance degradation,” in Proc. DATE,pp.75-80.
  7. Marculescu D K-C, Wu and (2011), “Aging-aware timing analysis and Optimization considering path sensitization,”in proc. DATE, pp.1-6.
  8. Y-S, Su, D-C, Wang, S-c, Chang, and Marek- Sadowska M (2011), “performance optimization using variable-latency design style,” IEEE Trans. Very large scale integr.(VLSI) Syst, vol.19, No.10, pp.1874-1883.
  9. M-C, Wen , s-j, Wang, and Y-n, Lin (2005), “Low power parallel Multiplier With column by passing,” in proc, IEEE ISCAS, pp.1638- 1641.
  10. Zafar et al S (2006), “A comparative study of NBTI and PBTI (charge trapping) in sio2/Hfo2 stacks with FUSI, Tin,Re gates,” in Proc. IEEE symp. VLSI Technol. Dig.Tech.Papers,2006,pp.23-25.
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