Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : D KayalVizhi | G Vallathanunnamed

Volume 03 Issue 06 2016

ISSN no:  2348-3121

Page no: 209-213

Abstract – This paper proposes a implementation of nano-level CMOS technology for power and area optimization in shift register using pulsed latches. This techniques used to ensure low power usage and area efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches. A shift register using pulsed latches was fabricated using 90nm CMOS process. In chip implementation, SSASPL (static differential sense amp shared pulse latch) which is the smallest latch, is selected. The size(W/L) of the transistor in pulsed latch are reduced by scaling. Scaling the transistor size decreases both the width (w) and gate length (l). By fabricating the chip at 90nm CMOS process, the core area and power consumption are reduced compared with the conventional shift register with flip-flop.

Keywords – Area-efficient, flip-flop, pulsed clock, pulsed latch, shift register


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