Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : T Sivalingam | P Naresh Kumar  unnamed

Volume 03 Issue 06 2016

ISSN no:  2348-3121

Page no: 17-20

Abstract – Memory based structures are used in many kind of digital signal processing (DSP) application. Memory-based structures are better performance in area minimization compare with multiply-accumulate structures and have many other advantages like reduced latency since the memory-access-time is much shorter than the usual multiplication-time compared to the conventional multipliers. The multiplier uses LUT’s as memory for their computations. The anti-symmetric product coding (APC) and odd-multiple-storage (OMS) techniques were used for look-up-table (LUT) in adaptive FIR filter. Memory-based structure such as APC and OMS techniques are used for efficient Multiplication. Hence, the combination of these two techniques provides reduction in LUT size to one fourth in adaptive FIR filter when compared with the conventional Look up Table (LUT) of adaptive FIR filter.

Keywords— Look up Table (LUT); anti-symmetric product coding (APC); odd-multiple-storage (OMS; distributed arithmetic (DA) 


  1. A. Antonion, Digital Filters: Analysis, Design, and Applications, McGraw-Hill, New York, 1993.
  2. H.T. Kung, Why systolic architecture? IEEE Computer 15 (1) (1982) 37–45.
  3. S. Yu, E.E. Swartzlander, DCT implementation with distributed arithmetic, IEEE Transactions on Computers 50 (9) (2001) 985–991.
  4. Hanho Lee, Gerald E. Sobelman, FPGA-based digit-serial CSD FIR filter for image signal format conversion, Microelectronics Journal 33 (5–6) (2002) 501–508.
  5. Valeria Garofalo, Fixed-width multipliers for the implementation of efficient digital FIR filters, Microelectronics Journal 39 (12) (2008) 1491–1498.
  6. Lei Zhang, Tadeusz Kwasniewski, FIR filter optimization using bit-edge equalization in high-speed backplane data transmission, Microelectronics Journal 40 (10) (2009) 1449–1457.
  7. M. A. M. Eshtawie and M. Othman, On-line DA-LUT architecture for high-speed high-order digital FIR filters, in: Proceedings of the IEEE International Conference on Communication Systems (ICCS), Singapore, November. 2006.
  8. J. P. Choi, S.-C. Shin, and J.-G. Chung, Efficient ROM size reduction for distributed arithmetic, in: Proceedings of the IEEE International Symposium Circuits Systems (ISCAS), May 2000, pp. 61–64.
  9. Sanjay, Attri B. S., Sohi, and Y. C. Chopra, Efficient design of application specific DSP cores using FPGAs, in: International Conference on ASIC Proceedings, 2001, pp. 462-466.
  10. Kim Kyung-Saeng, Kwyro Lee, Low-power and area efficient FIR filter implementation suitable for multiple tape, IEEE Transactions on VLSI Systems 11 (1) (February 2003).
Scroll Up