IJMTES – CARRY SELECT ADDER DESIGN USING D-LATCH WITH LESS DELAY AND MORE POWER EFFICIENT

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : O Mohana Chandrika | B Alekya Hima Bindu  unnamed

Volume 03 Issue 07 2016

ISSN no:  2348-3121

Page no: 109-113

Abstract – Ripple Carry Adder had a smaller area while having lesser speed, in contrast to which Carry Select Adders are high speed but posses a larger area. And a Carry Look Ahead Adder is in between the spectrum having a proper trade off between time and area complexities. Proposed logic block as a D latch with replacing RCA block in conventional design to evaluate the power consumption and area. In order to minimize area and power of 16 bit carry select adder we have replaced a BEC with D latch.   

Keywords— CSLA, D-Latch, BEC, RCA 

Reference

  1. Yajun. He, C. H. Chang, and J. Gu, “An area-efficient 64-bit square root carry select adder for low power application,” in Proc. IEEE Int. Symp. Circuits Syst., 2005, vol. 4, pp. 4082–4085.
  2. B. Ramkumar, H.M. Kittur, and P. M. Kannan, ―ASIC implementation of modified faster carry save adder,‖ Eur. J. Sci. Res., vol. 42, no. 1, pp. 53–58, 2010.
  3. B. Ramkumar and H.M. Kittur, “Low-power and area-efficient carry-select adder,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2pp. 371–375, Feb. 2012.
  4. Area–Delay–Power Efficient Carry-Select Adder Basant Kumar Mohanty, Senior Member, IEEE, and Sujit Kumar Patel,IEEE Transaction On CircuitAndSystem-i:Express Briefs, Vol 61, No 6, June 2014.
  5. Y.Kim and L-S Kim, “64-bit carry select adder ”IEEETransactions On Circuits And Systems-Ii: Express Briefs, Vol. 61, No. 6, June 2014.
  6. S.Manju and V. Sornagopal, “An efficient SQRT architecture of carry select adder design by common Boolean logic,” in Proc. VLSI ICEVENT, 2013,pp. 1–5.
  7. B.Parhami, Computer Arithmetic: Algorithms and Hardware Designs,2nd ed. NewYork, NY, USA: Oxford Univ. Press, 2010.
  8. R.UMA,VidyaVijayan, M. Mohanapriya, Sharon Paul2 ,”Area, Delay and Power Comparison of Adder Topologies” International Journal of VLSI design Communication Systems (VLSICS) Vol.3, No.1, February 2012.
  9. O. J. Bedrij, “Carry-select adder,” IRE Trans. Electron. Comput.,vol. EC-11, no. 3, pp. 340–344, Jun. 1962.
  10. A. P. Chandrakasan, N. Verma, and D. C. Daly, “Ultralow-power electronics for biomedical applications,” Annu. Rev. Biomed. Eng., vol. 10, pp. 247–274, Aug. 2008.
  11. B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs,2nded.New York, NY, USA: Oxford Univ. Press, 2010.
  12. K. K. Parhi, VLSI Digital Signal Processing. New York, NY, USA:Wiley,1998.
  13. J. M. Rabaey, Digital Integrated Circuits,” IEEE Trans. on VLSI Systems, 2003.
  14. O. J. Bedrij, ―Carry-select adder,‖ IRE Trans. Electron. Comput., pp. 340–344, 1962.
  15. I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin, and Chien-Chang Peng ,“ An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term” in Proceedings of International MultiConference of Engineers and Computer sciencentist 2012 Vol II, IMECS 2012, March 14-16, 2012, Hong-Kong.