Journal Title : International Journal of Modern Trends in Engineering and Science
Volume 03 Issue 08 2016
ISSN no: 2348-3121
Page no: 35-39
Abstract – Now a days the entire world is running towards digitalization process in every field as digitalization is rapidly becoming one of the standard form of processing, storage and transmission of information. Digitalization is nothing but the conversion of traditional analog data into digital format.in that scenario we necessitate a converter to change the analog data .so, in essential we go for ADC’s. The want of analog to digital converters with very-low power, area efficient and excessive speed is giving more chance to the use of dynamic regenerative comparators to increase the speed and power efficiency. Clocked comparators are regularly referred to as dynamic comparators. Dynamic double tail comparators are compared in terms of their power, speed and delay. The accuracy of comparators that is defined by using its electricity intake and speed is of eager interest in attaining over all better performance of ADCs. In the domain of signal processing with low power VLSI, the function of ADC device is crucial.Many high speed ADCs, such as flash ADCs, require excessive speed, low power comparators with small chip area. Compared with the double tail comparator in the proposed comparator both the power consumption and delay time are substantially reduced. Design has particularly focused on delay of double-tail comparator, which are called clocked regenerative comparator. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the primary contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator layout. Based on the existing analysis, a new dynamic comparator is proposed, where the circuit of traditional double tail dynamic comparator is altered for low power and fast operation even in small supply voltages. Here by adding a few transistors, the power consumptions can be reduced drastically. Post–layout simulation using 90nm CMOS technology confirms the analysis results of the proposed dynamic comparator.
Keywords— Analog to digital comparators, Clocked comparators, Dynamic double tail comparator, Flash ADC, Dynamic comparator
- B. Goll and H. Zimmermann, “A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 11, pp. 810–814, Nov. 2009.
- S. U. Ay, “A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS,” Int. J. Analog Integr. Circuits Signal Process, vol. 66, no. 2, pp. 213–221, Feb. 2011.
- A. Mesgarani, M. N. Alam, F. Z. Nelson, and S. U. Ay, “Supply boosting technique for designing very low-voltage smixed-signal circuits in standard CMOS,” in Proc. IEEE Int. Midwest Symp. Circuits Syst.Dig. Tech. Papers, Aug. 2010, pp. 893–896.
- B. J. Blalock, “Body-driving as a Low-Voltage Analog Design Technique for CMOS technology,” in Proc. IEEE Southwest Symp. Mixed-SignalDesign, Feb. 2000, pp. 113–118.
- M. Maymandi-Nejad and M. Sachdev, “1-bit quantiser with rail to rail input range for sub-1V ∆∑ modulators,” IEEE Electron. Lett., vol. 39, no. 12, pp. 894–895, Jan. 2003.
- Y. Okaniwa, H. Tamura, M. Kibune, D. Yamazaki, T.-S. Cheung, J. Ogawa, N. Tzartzanis, W. W. Walker, and T. Kuroda, “A 40Gb/s CMOS clocked comparator with bandwidth modulation technique,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1680–1687, Aug. 2005.
- R. Gregorian, Introduction to CMOS Op-Amps and Comparators (A Wiley-Interscience Publication (Wiley, New York, 1999)
- P. Nuzzo, F. D. Bernardinis, P. Terreni, and G. Van der Plas, “Noise analysis of regenerative comparators for reconfigurable ADC architectures,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 1441–1454, Jul. 2008.
- J. Kim, B. S. Leibowits, J. Ren, and C. J. Madden, “Simulation and analysis of random decision errors in clocked comparators,” IEEE Trans.Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp. 1844–1857, Aug. 2009.
- P. M. Figueiredo and J. C. Vital, “Kickback noise reduction technique for CMOS latched comparators,” IEEE Trans. Circuits Syst. II, Exp.Briefs, vol. 53, no. 7, pp. 541–545, Jul. 2006.
- D. Shinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, “A double-tail latch-type voltage sense amplifier with 18ps Setup+Hold time,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp. 314–315.
- A. Nikoozadeh and B. Murmann, “An analysis of latched comparator offset due to load capacitor mismatch,” IEEE Trans. Circuits Syst.II, Exp. Briefs, vol. 53, no. 12, pp. 1398–1402, Dec. 2006.