IJMTES – DESIGN OF CONSTANT MULTIPLIER ARCHITECTURE FOR FIR FILTER BASED ON SUB-SUBTRACTION ALGORITHM

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : Divya.P | Valluvan.K.R  unnamed

Volume 03 Issue 08 2016

ISSN no:  2348-3121

Page no: 18-21

Abstract – FIR filter has wide application as a component in any digital signal processing, image and video processing, wireless communication and biomedical signal processing systems. Significant applicability of an efficient reconfigurable FIR filter motivates the system designer to develop the chip with low cost, power, and area along with the capability to operate at very high speed. In existing methods, an efficient fixed point reconfigurable FIR filter is implemented using Vertical-horizontal Binary Common Sub-expression Elimination (VHBCSE) algorithm. The area and power are increased by the use of adders. In the proposed method, subtractor will be used instead of adders. The design is coded in Very High Speed Integrated circuit Hardware Description Language (VHDL) and simulated in ModelSim and synthesized in Electronic Design Automation (EDA) tool Xilinx_ISE 9.2i. The subtractor is proposed by sub-subtraction algorithm and its area, delay and power be compared with that of the existing method. 

Keywords— FIR filter, VHBCSE, Fixed point reconfigurable FIR filter, sub-subtraction algorithm 

Reference

  1. S. J. Darak, S. K. P. Gopi, V. A. Prasad and E. Lai, “Low-complexity reconfigurable fast filter bank for multi-standard wireless receivers”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 5, pp. 1202-1206, May 2014.
  2. Hatai, I. Chakrabarti, and S. Banerjee, “An efficient VLSI architecture of a reconfigurable pulse-shaping FIR interpolation filter for multi-standard DUC,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., May 2014.
  3. A. Hema Malini, C. Srimathi, “Low complexity digit serial FIR filter by multiple constant multiplication algorithms,” International Journal of Research in Engineering and Technology (IJRET), vol. 3, Issue: 04, April 2014.
  4. Indranil Hatai, Indrajit Chakrabarti and Swapna Banerjee, “An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis”, IEEE Trans. Circuits and Systems I, Vol. 62, No.4, pp. 421-425,April 2014.
  5. Y. C. Lim, J. B. Evans and B. Liu, “Decomposition of binary integers into signed power-of-two terms”, IEEE Trans. Circuits and Systems, Vol. 38, No. 6, pp. 667–672, June 1991.
  6. J. L. Nunez-Yanez, T. Spiteri and G. Vafiadis, “Multi-standard reconfigurable motion estimation processor for hybrid video codecs”, IET Comput. Digit. Tech., Vol. 5, no. 2, pp. 73–85, March 2011.
  7. Y. Pan and P. K. Meher, “Bit-level optimization of adder-trees for multiple constant multiplications for efficient FIR filter implementation”, IEEE Trans. Circuits Syst. I, Vol. 61, no. 2, pp. 455–462, Feb. 2014.
  8. H. Samueli H., “An improved search algorithm for the design of multiplier less FIR filters with power-of-two coefficients”, IEEE Trans. Circuits Syst., Vol. 36, pp. 1044–1047, July 1989.
  9. S. W. Smith, “The Scientist and Engineer’s Guide to Digital Signal Processing”, San Diego: California Technical Publications, 1997.
  10. M. Thenmozhi, N. Kirthika, “Analysis of efficient architectures for FIR filters using common subexpression elimination algorithm”, International Journal of Scientific & Technology Research, volume 1, Issue 4, May 2012.
  11. C. Y. Yao, W. C. Hsia and Y. H. Ho Y. H., “Designing hardware-efficient fixed-point FIR filters in an expanding subexpression space”, IEEE Trans. Circuits and Systems I, Vol. 61, pp. 202–212, Jan, 2014.