Journal Title : International Journal of Modern Trends in Engineering and Science
Volume 03 Issue 08 2016
ISSN no: 2348-3121
Page no: 18-21
Abstract – FIR filter has wide application as a component in any digital signal processing, image and video processing, wireless communication and biomedical signal processing systems. Significant applicability of an efficient reconfigurable FIR filter motivates the system designer to develop the chip with low cost, power, and area along with the capability to operate at very high speed. In existing methods, an efficient fixed point reconfigurable FIR filter is implemented using Vertical-horizontal Binary Common Sub-expression Elimination (VHBCSE) algorithm. The area and power are increased by the use of adders. In the proposed method, subtractor will be used instead of adders. The design is coded in Very High Speed Integrated circuit Hardware Description Language (VHDL) and simulated in ModelSim and synthesized in Electronic Design Automation (EDA) tool Xilinx_ISE 9.2i. The subtractor is proposed by sub-subtraction algorithm and its area, delay and power be compared with that of the existing method.
Keywords— FIR filter, VHBCSE, Fixed point reconfigurable FIR filter, sub-subtraction algorithm
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