IJMTES – MULTIPLIER DESIGN WITH RAZOR FLIP FLOP & AHL

Journal Title : International Journal of Modern Trends in Engineering and Science

Author’s Name : S Surya | Dr C Vivekanandan | Kamatchi  unnamed

Volume 03 Issue 09 2016

ISSN no:  2348-3121

Page no: 58-62

Abstract – Digital multipliers are the basic model for all arithmetic and functional units. The  performance of all systems depends on the throughput of the multiplier. The negative bias temperature instability effect occurs when a pMOS transistor is under negative bias, increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect.Digital multipliers are among the most critical arithmetic functional units in many applications, such as Fourier transform, discrete cosine transforms and digital filtering.The throughput of these applications depends on multipliers, and if the multipliers are too slow, the performance of entire circuits will be reduced.This paper proposed a variable-latency multiplier design with the AHL. The multiplier is able to adjust the AHL to mitigate performance degradation due to increased delay. The experimental results show that our proposed architecture with 16× 16 column-bypassing  multipliers  attain 180 mw power estimation compared with fixed latency of 192 mw and 16× 16 row bypassing multiplier attain 179 mw power estimation compared with fixed latency of 199 mv . 

Keywords— Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability(PBTI), reliable multiplier, variable latency design

Reference

  1. Y. Cao. (2013). Predictive Technology Model (PTM) and NBTI Model [Online]. Available: http://www.eas.asu.edu/∼ptm
  2. S. Zafar et al., “A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates,” in Proc. IEEE Symp. VLSI Technol. Dig. Tech. Papers, 2006, pp. 23–25.
  3. S. Zafar, A. Kumar, E. Gusev, and E. Cartier, “Threshold voltage instabilities in high-k gate dielectric stacks,” IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp. 45–64, Mar. 2005.
  4. H.-I. Yang, S.-C.Yang, W. Hwang, and C.-T. Chuang, “Impacts of NBTI/PBTI on timing control circuits and degradation tolerant design in nanoscale CMOS SRAM,” IEEE Trans. Circuit Syst., vol. 58, no. 6, pp. 1239–1251, Jun. 2011.
  5. R. Vattikonda, W. Wang, and Y. Cao, “Modeling and miimization of pMOS NBTI effect for robust naometer design,” in Proc. ACM/IEEEDAC, Jun. 2004, pp. 1047–1052.
  6. H. Abrishami, S. Hatami, B. Amelifard, and M. Pedram, “NBTI-aware flip-flop characterization and design,” in Proc. 44th ACM GLSVLSI,2008, pp. 29–34
  7. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “NBTI- aware synthesis of digital circuits,” in Proc. ACM/IEEE DAC, Jun. 2007, pp. 370–375.
  8. A. Calimera, E. Macii, and M. Poncino, “Design techniqures for NBTItolerant power-gating architecture,” IEEE Trans. Circuits Syst., Exp. Briefs, vol. 59, no. 4, pp. 249–253, Apr. 2012.
  9. K.-C. Wu and D. Marculescu, “Joint logic restructuring and pin reordering against NBTI-induced performance degradation,” in Proc. DATE, 2009, pp. 75–80.
  10. Y. Lee and T. Kim, “A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs,” in Proc. ASPDAC, 2011, pp. 603–608.
  11. M. Basoglu, M. Orshansky, and M. Erez, “NBTI-aware DVFS: A new approach to saving energy and increasing processor lifetime,” in Proc. ACM/IEEE ISLPED, Aug. 2010, pp. 253–258.
  12. K.-C. Wu and D. Marculescu, “Aging-aware timing analysis and optimizationconsidering path sensitization,” in Proc. DATE, 2011, pp. 1–6.
  13. K. Du, P. Varman, and K. Mohanram, “High performance reliablevariable latency carry select addition,” in Proc. DATE, 2012,pp. 1257–1262.
  14. A. K. Verma, P. Brisk, and P. Ienne, “Variable latency speculativeaddition: A new paradigm for arithmetic circuit design,” in Proc. DATE,2008, pp. 1250–1255.
  15. D. Baneres, J. Cortadella, and M. Kishinevsky, “Variable-latency designby function speculation,” in Proc. DATE, 2009, pp. 1704–1709.
  16. Y.-S. Su, D.-C.Wang, S.-C. Chang, and M. Marek-Sadowska, “Performance”optimization using variable-latency design style,” IEEETrans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 10, pp. 1874–1883, Oct. 2011.
  17. N. V. Mujadiya, “Instruction scheduling on variable latency functionalunits of VLIW processors,” in Proc. ACM/IEEE ISED, Dec. 2011,pp. 307–312.
  18. M. Olivieri, “Design of synchronous and asynchronous variable-latencypipelined multipliers,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,vol. 9, no. 4, pp. 365–376, Aug. 2001.
  19. D. Mohapatra, G. Karakonstantis, and K. Roy, “Low-power processvariatio tolerant arithmetic units using input-based elastic clocking,” in Proc. ACM/IEEE ISLPED, Aug. 2007, pp. 74–79.
  20. Y. Chen, H. Li, J. Li, and C.-K.Koh, “Variable-latency adder (VL-Adder): New arithmetic circuit design practice to overcome NBTI,”inProc. ACM/IEEE ISLPED, Aug. 2007, pp. 195–200.
  21. Y. Chen et al., “Variable-latency adder (VL-Adder) designs for low power and NBTI tolerance,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 11, pp. 1621–1624, Nov. 2010.
  22. M.-C. Wen, S.-J.Wang, and Y.-N. Lin, “Low power parallel multiplier with column bypassing,” in Proc. IEEE ISCAS, May 2005,pp. 1638–1641.
  23. J. Ohban, V. G. Moshnyaga, and K. Inoue, “Multiplier energy reduction through bypassing of partial products,” in Proc. APCCAS, 2002,pp. 13–17.
  24. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, “Impact of NBTI on the temporal performance degradation of digital circuits,” IEEE Electron Device Lett., vol. 26, no. 8, pp. 560–562, Aug. 2005.
  25. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, “Negative bias temperature instability: Estimation and design for improved reliability of nanoscale circuit,” IEEE Trans. Comput.-Aided Des. Integr.Circuits Syst., vol. 26, no. 4, pp. 743–751, Apr. 2007.
  26. R. Vattikonda, W. Wang, and Y. Cao, “Modeling and minimization of pMOS NBTI effect for robust nanometer design,” in Proc. 43rd ACM/IEEE DAC, Aug. 2006, pp. 1047–1052.
  27. D. Ernst et al., “Razor: A low-power pipeline based on circuit-level timing speculation,” in Proc. 36th Annu. IEEE/ACM MICRO, Dec. 2003, pp. 7–18.