Journal Title : International Journal of Modern Trends in Engineering and Science
Volume 03 Issue 09 2016
ISSN no: 2348-3121
Page no: 58-62
Abstract – Digital multipliers are the basic model for all arithmetic and functional units. The performance of all systems depends on the throughput of the multiplier. The negative bias temperature instability effect occurs when a pMOS transistor is under negative bias, increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect.Digital multipliers are among the most critical arithmetic functional units in many applications, such as Fourier transform, discrete cosine transforms and digital filtering.The throughput of these applications depends on multipliers, and if the multipliers are too slow, the performance of entire circuits will be reduced.This paper proposed a variable-latency multiplier design with the AHL. The multiplier is able to adjust the AHL to mitigate performance degradation due to increased delay. The experimental results show that our proposed architecture with 16× 16 column-bypassing multipliers attain 180 mw power estimation compared with fixed latency of 192 mw and 16× 16 row bypassing multiplier attain 179 mw power estimation compared with fixed latency of 199 mv .
Keywords— Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability(PBTI), reliable multiplier, variable latency design
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