IJMTES – MISMATCH ERRORS MINIMIZATION IN TIME INTERLEAVED ADC DESIGN

Journal Title : International Journal of Modern Trends in Engineering and Science

Paper Title : MISMATCH ERRORS MINIMIZATION IN TIME INTERLEAVED ADC DESIGN

Author’s Name : Poornima P | Gowri Shankar V  unnamed

Volume 03 Issue 09 2016

ISSN no:  2348-3121

Page no: 113-117

Abstract – The signals in the world are inherently analog. But the processing of analog signals is very difficult. Hence, it is required to convert Analog to Digital Signals by the use of ADC. In the existing ADC, time interleaved ADC is analyzed. In time interleaved ADC, several ADCs are connected in parallel to produce the correct accuracy. Even though it produces correct accuracy. It has errors such as gain, offset and time skew. To overcome this in proposed method, a new ADC is designed by using PLL. By using PLL, the mismatch errors are greatly reduced. The proposed method is simulated using Modelsim 10.1b and its performance parameter such as gain, offset values is analyzed.  

Keywords— ADC, PLL, Time Interleaved ADC, Offset, Time Skew

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