IJMTES – DESIGN OF LOW COMPLEXITY FAULT TOLERANT PARALLEL FFTS USING PARTIAL

Journal Title : International Journal of Modern Trends in Engineering and Science

Paper Title : DESIGN OF LOW COMPLEXITY FAULT TOLERANT PARALLEL FFTS USING PARTIAL

Author’s Name : Senbagavalli K | Nimsha K Runnamed

Volume 04 Issue 01 2017

ISSN no:  2348-3121

Page no: 7-10

Abstract – As signal-processing circuits become more complex, it is common to find several filters or FFTs operating in parallel. Soft errors pose a reliability threat to modern electronic circuits. This makes protection against soft errors a requirement for many applications. Communications and signal processing systems are no exceptions to this trend. For some applications, an interesting option is to use algorithmic-based fault tolerance (ABFT) techniques that try to exploit the algorithmic properties to detect and correct errors. Signal processing and communication applications are well suited for ABFT. One example is fast Fourier transforms (FFTs) that are a key building block in many systems. Several protection schemes have been proposed to detect and correct errors in FFTs. Among those, probably the use of the Parseval or sum of squares checks is the most widely known. In modern communication systems, it is increasingly common to find several blocks operating in parallel. Recently, a technique that exploits this fact to implement fault tolerance on parallel filters has been proposed. In this brief, this technique is first applied to protect FFTs. Then, two improved protection schemes that combine the use of error correction codes and Parseval checks are proposed and evaluated. The results show that the proposed schemes can further reduce the implementation cost of protection.

Reference

  1. B. Shim and N. R. Shanbhag, “Energy-efficient soft error-tolerant digital signal processing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 4, pp. 336–348, Apr. 2006.
  2. P. Reviriego, S. Pontarelli, C. J. Bleakley, and J. A. Maestro, “Area efficient concurrent error detection and correction for parallel filters,” IET Electron. Lett., vol. 48, no. 20, pp. 1258–1260, Sep. 2012.
  3. Z. Gao et al., “Fault tolerant parallel filters based on error correction codes,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 2, pp. 384–387, Feb. 2015.
  4. P. Reviriego, C. J. Bleakley, and J. A. Maestro, “A novel concurrent error detection technique for the fast Fourier transform,” in Proc. ISSC, Maynooth, Ireland, Jun. 2012, pp. 1–5.
  5. S.-J. Wang and N. K. Jha, “Algorithm-based fault tolerance for FFT networks,” IEEE Trans. Comput., vol. 43, no. 7, pp. 849–854, Jul. 1994.