IJMTES – LOW POWER AND LOW DELAY BUFFER USING SRAM DESIGN IN 180NM TECHNOLOGY

Journal Title : International Journal of Modern Trends in Engineering and Science

Paper Title : LOW POWER AND LOW DELAY BUFFER USING SRAM DESIGN IN 180NM TECHNOLOGY

Author’s Name : Dr N J R Muniraj | K Vishnuvarthini
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Volume 04 Issue 11 2017

ISSN no:  2348-3121

Page no: 20-22

Abstract – This paper addresses the issues of power dissipation and propagation delay in CMOS tapered buffer circuits which are frequently used to drive large capacitive loads. Usually large fan out capacitive loads need to be driven by a single gate without compromising high speed. With technology scaling, it is becoming increasingly challenging to maintain the yield while attempting to reduce the leakage power of SRAMs. The sources of SRAM power are the sum of the power consumed by decoders, memory array, write drivers, Sense amplifiers, and I/O line drivers. This paper focus mainly on driving that large capacitive load, in this regard we introduce some driving circuits known as buffers. So the main objective of this paper is to minimize delay of the overall circuit and power consumption while driving large capacitive loads using buffers. Hence the work is carried out in cadence Virtuoso Spectre in 180 nm technology.

Keywords – CMOS, Tapered Buffer, Leakage Power, SRAM Peripheral

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