IJMTES – DESIGN OF EFFICIENT AND HIGH PERFORMANCE SHIFT REGISTER USING DIFFERENT TECHNIQUES

Journal Title : International Journal of Modern Trends in Engineering and Science

Paper Title : DESIGN OF EFFICIENT AND HIGH PERFORMANCE SHIFT REGISTER USING DIFFERENT TECHNIQUES  

Author’s Name : S Premaunnamed

Volume 04 Issue 02 2017

ISSN no:  2348-3121

Page no: 6-9

Abstract – Low power and area is one of the main objective in all  VLSI circuts. The Shift register is the basic building block in VLSI Design. It is commonly used in many applications. Clock signal is the major factor  of power dissipation in synchronous circuits because of high frequency and load. The architecture of shift register is quite simple. The M bit shift register can be is composed of M data flip-flops. The smallest flip-flops is suitable for designing of shift register to reduce the area and power consumption. A methodology has been developed which uses latches triggered with pulse clock waveforms. With this methodology, timing analysis and timing optimization to a latch design while reducing the power of the clock networks can obtain. A latch can capture data during the sensitive time determined by the width of clock waveform. If the pulse clock waveform triggers a latch, the latch is synchronized with the clock similarly to edge-triggered flip-flop because the rising and falling edges of the pulse clock are almost identical in terms of timing.

Keywords— Pulsed Clock; Latch; Shift Register

Reference

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