Journal Title : International Journal of Modern Trends in Engineering and Science
Paper Title : FLOATING POINT THREE TERM ADDER REDUCES AREA AND INCREASES THE SPEED BY NOVEL APPROACH
Volume 04 Issue 02 2017
ISSN no: 2348-3121
Page no: 102-105
Abstract – This paper presents an area efficient architecture for fused floating point addition using three terms. The first step of fused floating point addition is exponent comparison and significant alignment which occupies a major proportion of area in the overall architecture. Reduction in area is achieved by replacing exponent processing , significant alignment block and mantissa addition block of the existing fused floating point three term adder architecture with blocks having reduced area and comparable speed .The blocks proposed utilizes less hardware compared to the existing blocks without any compromise in the performance. The performance measures are evaluated using a specific tool and reduction in area is observed from the proposed work.
Keywords – Area Efficient, Exponent Compare, Significant Alignment, Ling Adder
- IEEE Standard for Floating-Point Arithmetic, ANSI/IEEE Standard 754-2008, IEEE, Inc., 2008.
- T. Lang and J.D. Bruguera, “Floating-point fused multiply-add with reduced latency,” IEEE Trans. Computers, vol. 53, pp. 988–1003, 2004.
- H. H. Saleh and E. E. Swartzlander, Jr., “A floating-point fused add subtract unit,” in Proc. 51st IEEE Midwest Symp. Circuits Syst., 2008,pp. 519–522.
- J. Sohn and E. E. Swartzlander, Jr., “Improved architectures for a fused floating-point add-subtract unit,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 10, pp. 2285–2291, Oct. 2012.
- H. H. Saleh and E. E. Swartzlander, Jr., “A floating-point fused dot product unit,” in Proc. IEEE Int. Conf. Computer Des., 2008, pp.427–431.
- J. Sohn and E. E. Swartzlander, Jr., “A fused floating-point three-term adder,” in IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 10, pp. 2842–2850, Oct. 2014.
- A. Tenca, “Multi-operand floating-point addition,” in Proc. 21st Symp. Computer Arithmetic, 2009, pp. 161–168.
- Y. Tao, G. Deyuan, F. Xiaoya, and R. Xianglong, “Three-operand floating-point adder,” in Pro. 12th IEEE Int. Conf. Comput. Inf Technol., 2012, pp. 192–196.
- Jongwook Sohn, “Improved architecture for fused floating-point arithmetic units,” Ph.D. dissertation, University of Texas, Austin,2013.
- P. M. Seidel and G. Even, “Delay-optimized implementation of IEEE floating-point addition,” IEEE Trans. Computers, vol. 53, no. 2, pp.97–113, Feb. 2004.
- M. S. Schmookler and K. J. Nowka, “Leading zero anticipation and detection-a comparison of methods,” in Proc. 15th IEEE Symp. Computer Arithmetic, 2001, pp. 7–12.
- V. G. Oklobdzija, “An algorithmic and novel design of a leading zero detector circuit comparison with logic synthesis,” IEEE Trans. VLSI Syst., vol. 2, no. 1, pp. 124–128, Mar. 1994.
- G. Dimitrakopoulos, K. Galanopoulos, C. Mavrokefalidis, and D.Nikolos , “Low- power leading zero counting and anticipation logic for high-speed floating point units,” IEEE Trans. VLSI Syst., vol. 16, no. 7, pp. 837–850, Jul. 2008.
- J. D. Bruguera and T. Lang, “Leading-one prediction with concurrent position correction,” IEEE Trans. Computers, vol. 48, no. 10, pp.1083–1097, Oct. 1999.
- R.Ji.Z.Ling,X.Zeng,B.Sui,L.Chen,J.Zhang,Y. Feng, and G. Luo, “Leading-one prediction with concurrent position correction,” IEEE Trans. Comput., vol. 58, no. 12, pp. 1726–1727, Dec. 2009.
- N.Poornima, V.S.Kanchana Bhaskaran, “Area efficient hybrid parallel prefix adders”.
- Giorgos Dimitrakopoulous,Dimitris Nikolos, “High-speed parallel prefix VLSI ling adders,” IEEE Trans. Comput., vol. 54, no. 2, pp. 225–231, Feb. 2005.
- P. Kornerup, “Correcting the normalization shift of redundant binary representations,” IEEE Trans. Computers, vol. 58, pp. 1435–1439,2009.
- G. Even and P.M. Seidel, “A comparison of three rounding algorithms for IEEE floating-point multiplication,” IEEE Trans. Comput., vol. 49,pp. 638–650, 2000.