IJMTES – CONTROLLING STATIC POWER LEAKAGE IN 7T SRAM CELL USING POWER GATING TECHNIQUE

Journal Title : International Journal of Modern Trends in Engineering and Science

Paper Title : CONTROLLING STATIC POWER LEAKAGE IN 7T SRAM CELL USING POWER GATING TECHNIQUE

Author’s Name : Mr T Mani | P Praveen | P Soundararajan | M Suresh | D Prakashunnamed

Volume 04 Issue 04 2017

ISSN no:  2348-3121

Page no: 69-73

Abstract – Nowadays power leakage on-chip SRAM is a crucial part in many applications. In existing 7T SRAM cell with super cut-off word line technology static power leakage is reduced up to 26%. In proposed system static power leakage is further reduced by using power gating technique. Static power reduction using power gating technique can be providing better performance than the convectional 7T SRAM and in super cut-off word line technique. Power gating technique can of two types coarse grain and fine gain technique. In proposed system uses coarse grained technique. Header coarse grained and footer coarse grained used to reduce the static power leakage in 7T SRAM. By using header coarse grained technique is reduces more power when compared to footer coarse grain technique.

Keywords— Power gating technique, super cut-of word line, course grained technique, fine gain technique, header and footer course grained technique

References

  1. J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital intergrated circuits: A Design Perspective, 2nd ed. Prentice Hall, 2003.
  2. L. Villa, M. Zhang, and K. Asanovic, “Dynamic zero compression for cache energy reduction,” in Proc. 33rd Int. Symp. Microarchitecture Mzcro-33, 2000, pp. 214-220.
  3. M. Yoshimoto et al., “A 64kb CMOS RAM with divided word line structure,” in IEEE Int. Solid State Circuits Conj Tech. Digest, 1983, pp. 58-59.
  4. K. W. Mai et al., “Low-Power SRAM design using half-swing pulse-mode techniques,” IEEE J Solid State Circuits, vol. 33, pp. 659-1671, Nov. 1998.
  5. S. Hattori, and T. Sakurai, “90% Write power saving SRAM using sense-amplifying memory cell,” IEEE J Solid State Circuits, vol. 39, pp. 927-933, June 2004.
  6. A. Karandikar, and K. K. Parhi, “Low power SRAM design using hierarchical divided bit-line approach,” in Int. Conference Computer. Design, 1998, pp. 82-88.
  7. N. Azizi et al., “Low-leakage Asymmetric-Cell SRAM,” IEEE. Trans. Very Large Integrated Scale (VLSI) Syst., vol. 11, pp. 701-715, 2003.
  8. J. Hennessy, and D. Patterson, Computer Architecture: A Quantitative Approach, 3rd ed. Morgan Kaufmann, 2003.
  9. Seevinck et al., “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE J Solid-State Circuits, vol. 22, pp. 748-754, 1987.
  10. K. Zhang et al., “A SRAM design on 65nm CMOS technology with integrated leakage reduction scheme,” VLSI Circuits Sym. Tech. Digest, p294, Jun 2004.
Scroll Up