IJMTES – DESIGNING FIXED WIDTH RPR MULTIPLIER FOR LOW ERROR COMPENSATION USING IN MERGING OF IMAGES

Journal Title : International Journal of Modern Trends in Engineering and Science

Paper Title : DESIGNING FIXED WIDTH RPR MULTIPLIER FOR LOW ERROR COMPENSATION USING IN MERGING OF IMAGES

Author’s Name : S Hasma Shruthiunnamed

Volume 04 Issue 04 2017

ISSN no :  2348-3121

Page no: 109-111

Abstract – This paper presents an error compensation method using fixed width RPR(Reduced Precision Redundancy). We propose a new method called fixed width RPR for DSP applications. This fixed width multiplier is placed in ANT architecture to meet high speed, low power consumption and area efficiency. The fixed RPR is designed with compensation circuit for minimizing the occurrence of error. The nxn bit is used as a input. The partial product term is used in RPR block for input correction vector and trivial input modification vector to worse the truncation errors. To achieve more precise error compensation. Variable correction value is used the truncation error can be compensation circuit is minimized. This circuit can be use in applications of image processing. By using this multiplier we merge the two images into compressed single image

Key Words – Algorithmic noise tolerant (ANT), fixed-width multiplier, reduced-precision replica (RPR),voltage over scaling(VOS) and error correction block(EC)

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