IJMTES – DESIGN AND IMPLEMENTATION OF REVERSE CONVERTERS USING HYBRID PARALLEL PREFIX ADDER

Journal Title : International Journal of Modern Trends in Engineering and Science

Paper Title : DESIGN AND IMPLEMENTATION OF REVERSE CONVERTERS USING HYBRID PARALLEL PREFIX ADDER

Author’s Name : Ms U Sararawathi | Mrs V Vandhana
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Volume 04 Issue 06 2017

ISSN no:  2348-3121

Page no: 39-41

Abstract – Adders are the basic building block in the arithmetic circuits. The reverse converter is a key component in the residue number based arithmetic system. Usually the reverse converter design using the parallel prefix adders will provide high speed and delay reduction in arithmetic operations but it is not widely used since it suffers from higher power consumption. As a result, larger delay along with higher power consumption is obtained, which is the main drawback for any VLSI applications. In order to overcome this, Hybrid Parallel prefix network used instead of brent kung adder, kogge stone adder and Han Carlson adder. Therefore it reduces delay and power consumption also reduced the area. The proposed system introduces an improved HRPX and HMPE structure with hybrid BK and KS prefix networks. In this paper, we use a new prefix adder structure, this adder is a mixture three types of adders that is Brent-Kung ,Kogge-stone adder and han carlson adder.. The proposed design shows better performance in terms of power, area and delay

Keywords – Brent Kung Adder, Kogge Stone Adder, Han Carlson adder, High Speed, Power Consumption, Area Minimization

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