Journal Title : International Journal of Modern Trends in Engineering and Science


Author’s Name : Shankari C | Athira V S | Jagdesh Munnamed

Volume 04 Issue 08 2017

ISSN no:  2348-3121

Page no: 8-12

Abstract – Multiplication is one of the basic operation in digital signal processing, multimedia& microprocessor. Redundant binary multipliers are widely used for high speed multiplication. The conventional multiplier requires an additional redundant binary (RB) product because a error correcting word is generated by both radix-4 modified booth and encoding & RB encoding. Here a new RB radix-4 booth encoding partial product generator is used. RB multiplier is used in multiplier with operand without increasing the delay of partial product. It removes extra error correcting word (ECW) and saves one stage of redundant binary partial product (RBPP).The stage count is decreased. The power delay is reduced using the modified RB multiplier when comparing the conventional multiplier. Pipelining is used for removing additional stages in the process. Simulation results have been Multiplication operation product is obtained by adding partial product. It improves the area and power consumption. It results in the improvements of complexity and critical path delay for a RB multiplier.

Keywords – Redundant Binary (RB), Modified Booth, Partial Product (PP), Error Correcting Word (ECW), Redundant Binary Partial Product (RBPP)


  1. Xiaoping Cui, Weiqiang Liu Xin Chen, Earl E. Swartzlander, Jr., Life and Fabrizio Lombardi,” A Modified Partial Product Generator for Redundant Binary Multipliers”,,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52 0018-9340 (c) 2015.
  2. A. Avizienis, “Signed-digit number representations for fast parallel arithmetic,” IRE Trans. Electron. Computers, vol. EC-10, pp. 389–400, 1961.
  3. A. Booth, “A signed binary multiplication technique,” The Quarterly J. Mechanical and Applied Math., vol. 4, pp. 236-240, 1951
  4. C. Chang, J. Gu, and M. Zhang, “Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, pp. 1985–1997, 2004.
  5. D. Radhakrishnan and A. Preethy, “Low power CMOS pass logic 4-2 compressor for high-speed multiplication,” in Proc. IEEE Midwest Symp. Circuits Syst., vol. 3, pp. 1296–1298, 2000
  6. F. Lamberti, N. Andrikos, E. Antelo, and P. Montuschi, “Reducing the computation time in (short bit-width) two’s complement multipliers,” IEEE Trans. Computers, vol. 60, pp. 148-
  7. L. Ciminiera and P. Montuschi, “Carry-save multiplication schemes without final addition,” IEEE Trans. Computers, vol. 45, pp. 1050-1055,1996. 156, 2011.
  8. G. Wang and M. Tull, “A new redundant binary number to 2’scomplement number converter,” in Proc. Region 5 Conference: Annual Technical and Leadership Workshop, pp. 141-143, 2004.
  9. H. Edamatsu, T. Taniguchi, T. Nishiyama, and S. Kuninobu, “A 33 MFLOPS floating point processor using redundant binary representation,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 152–153, 1988.
  10. H. Makino, Y. Nakase, and H. Shinohara, “A 8.8-ns 54×54-bit multiplier using new redundant binary architecture,” in Proc. Int. Conf. Comput. Design (ICCD), pp. 202-205, 1993.
  11. H. Makino, Y. Nakase, H. Suzuki, H. Morinaka, H. Shinohara, and K. Makino, “An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture,” IEEE J. Solid-State Circuits, vol. 31, pp. 773-783, 1996.
  12. J. Kang and J. Gaudiot,“A simple high-speed multiplier design,” IEEE Trans. Computers, vol. 55, pp.1253-1258, 2006
  13. M. Ercegovac and T. Lang, “Comments on ‘a carry-free 54b×54b multiplier using equivalent bit conversion algorithm’,” IEEE J. Solid-State Circuits, vol. 38, pp. 160–161, 2003.
  14. M. Ercegovac and T. Lang, “On-the-fly conversion of redundant to conventional representations,” IEEE Trans. Computers, vol. C-36, pp. 895-897, 1987.
  15. M. Ercegovac and T. Lang, “Fast multiplication without carry propagate addition,” IEEE Trans. Computers, vol. C-39, pp. 1385-1390, 1990.
  16. N. Besli and R. Deshmukh, “A novel redundant binary signed digit (RBSD) Booth’s encoding,” in Proc. IEEE Southeast Conf., pp. 426–431, 2002.
  17. O. MacSorley, “High-speed arithmetic in binary computers,” IRE Proc., vol. 49, pp. 67–91, 1961.
  18. S. Kuang, J. Wang, and C. Guo, “Modified Booth multiplier with a regular partial product array,” IEEE Trans. Circuits Syst. II, vol. 56, pp. 404-408, 2009.
  19. W. Yeh and C. Jen, “High-speed Booth encoded parallel multiplier design,” IEEE Trans. Computers, vol. 49, pp. 692-701, 2000.
  20. Y. He and C. Chang, “A new redundant binary Booth encoding for fast 2-bit multiplier design,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, pp. 1192–1199, 2009