IJMTES – LOW POWER HIGH SPEED MODIFIED SQRT CSLA DESIGN USING D-LATCH & BK ADDER

Journal Title : International Journal of Modern Trends in Engineering and Science

Paper Title : LOW POWER HIGH SPEED MODIFIED SQRT CSLA DESIGN USING D-LATCH & BK ADDER

Author’s Name : Athira V S | Shankari C | R Arun Sekarunnamed

Volume 04 Issue 08 2017

ISSN no:  2348-3121

Page no: 13-17

Abstract – The basic building blocks of any processor is adders. In VLSI design the adders used as fundamental requirements to achieve high performance processors and multi-core devices. To acquire fast arithmetic functions in many processors, fastest adder carry select adder is used. Conventional CSLA designs like Modified SQRT CSLA (MCSLA) and Binary to Excess one Converter (BEC) based CSLA and are compared with proposed D-latch and Brent Kung based CSLA, which shows better performance in terms of delay and power. In this paper 16 bit carry select adder with different models have been analyzed based on parameters like speed, area of utilization and power. The design is written in Verilog Hardware Description Language (HDL) and synthesized using Xilinx ISE 14.5.

Keywords – Ripple carry adder (RCA), carry select adder, Square root CSLA, Modified SQRT CSLA, Brent Kung based Modified SQRT CSLA and D-latch Carry select adder.

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